1. Field of the Invention
The present invention relates to a voltage regulator which outputs a predetermined direct-current voltage and which restrains the direct-current voltage from extreme variation when a power supply voltage which is supplied to the voltage regulator is greatly changed. This is a counterpart of and claims priority to Japanese Patent Application No. 2004-57714 filed on Mar. 2, 2004, which is herein incorporated by reference.
2. Description of the Related Art
FIG. 1 is a circuit diagram for describing a voltage regulator which outputs a predetermined direct-current voltage of the related art. This voltage regulator includes a bias circuit 10 which outputs a high bias voltage Vbh and a low bias voltage Vbl, a reference voltage generator 20 which generates a reference voltage Vref based on which the predetermined direct-current voltage Vout is generated, a differential amplifier 30 and an output circuit 40 which outputs the predetermined direct-current voltage Vout and a comparison voltage Vcom.
The differential amplifier 30 outputs a control voltage Vcon based on a difference between the reference voltage Vref and the comparison voltage Vcom. The differential amplifier 30 has an N-conductive type Metal Oxide Semiconductor (hereinafter referred to as the “NMOS”) transistor 31 which receives the reference voltage Vref and an NMOS transistor 32 which receives the comparison voltage Vcom. The NMOS transistor 31 has a drain electrode coupled with a first electrical source terminal T1 through a P-conductive type MOS (hereinafter referred to as the “PMOS”) transistor 33. The NMOS transistor 32 has a drain electrode coupled with the first electrical source terminal T1 through a PMOS transistor 34. The NMOS transistors 31 and 32 respectively have source electrodes coupled with a node N1. An NMOS transistor 35 is coupled between the node N1 and a second electrical source terminal T2. The NMOS transistor 35 allows a constant current to pass through itself in accordance with the low bias voltage Vbl. The PMOS transistors 33 and 34 respectively have gate electrodes coupled with the drain electrode of the NMOS transistor 32. Also, the control signal Vcon is output from a node N2 which is coupled with the drain electrode of the NMOS transistor 31.
The output circuit 40 not only outputs the predetermined direct-current voltage Vout based on the control voltage Vcon but also generates the comparison voltage Vcom for the differential amplifier 30 based on the direct-current voltage Vout. The output circuit 40 includes a PMOS transistor 41 which is controlled by the control voltage Vcon, a diode-connected NMOS transistor 42 and an NMOS transistor 43 which is controlled by the low bias voltage Vbl, which are coupled in series between the first electrical source terminal T1 and the second electrical source terminal T2. The predetermined direct-current voltage Vout is output from a drain electrode of the diode-connected NMOS transistor 42, and the comparison voltage Vcom is output from a source electrode of the diode-connected NMOS transistor 42.
Details of the operations with respect to the above-mentioned voltage regulator are described below. Hereupon, for example, it is assumed that the first electrical source terminal T1 receives a first electrical source voltage V1 such as a power supply voltage Vcc and the second electrical source terminal T2 receives a second electrical source voltage V2 such as a ground voltage Vss. Furthermore, it is assumed that the power supply voltage Vcc changes in the range from 2.5V to 4.0V and the predetermined direct-current voltage Vout is 1.5V.
First of all, when the power supply voltage Vcc is 2.5V, the above-mentioned voltage regulator operates as described below.
When the reference voltage Vref (1.0V for example) output from the reference voltage generator 20 is higher than the comparison voltage Vcom from the output circuit 40, an ON-state resistance of the NMOS transistor 31 is decreased and an ON-state resistance of the NMOS transistor 32 is increased. Therefore, an electrical potential on the node N2 is decreased, that is, the control voltage Vcon which is provided to the gate electrode of the PMOS transistor 41 in the output circuit 40 is decreased. As a result, an ON-state resistance of the PMOS transistor 41 is decreased, and then, the direct-current voltage Vout and the comparison voltage Vcom are increased. On the other hand, when the reference voltage Vref is lower than the comparison voltage Vcom, the ON-state resistance of the NMOS transistor 31 is increased and the ON-state resistance of the NMOS transistor 32 is decreased. Therefore, the control voltage Vcon is increased. As a result, the ON-state resistance of the PMOS transistor 41 is increased, and then, the comparison voltage Vcom are decreased.
That is, the comparison voltage Vcom is adjusted to be equal to the reference voltage Vref by the above-mentioned feedback operation. Hereupon, for example, when the NMOS transistor 42 has a threshold voltage of 0.5V in a forward-biased direction, the predetermined direct-current voltage Vout of 1.5V is output from the output circuit 40, based on a sum of the reference voltage Vref (1.0V) and the threshold voltage (0.5V) of the NMOS transistor 42. At this time, if the PMOS transistor 41 has a threshold voltage of 0.5V in the forward-biased direction, the control voltage Vcon is substantially kept at 2.0V so that a voltage between a gate electrode and a source electrode of the PMOS transistor 41 can be substantially kept at the threshold voltage of the PMOS transistor 41.
Then, after the power supply voltage Vcc is changed from 2.5V to 4.0V, the reference voltage Vref is kept as it is and the control voltage Vcon is increased by a capacitance between the gate electrode and the source electrode of the PMOS transistor 41 responsive to the change of the power supply voltage Vcc. Therefore, the voltage between the gate electrode and the source electrode of the PMOS transistor 41 is still kept at the threshold voltage of the PMOS transistor 41. As a result, the predetermined direct-current voltage Vout and the comparison voltage Vcom are still kept at the voltages as before the change of the power supply voltage Vcc. That is, the direct-current voltage Vout is kept at the predetermined voltage without any changes before as well as after the change of the power supply voltage Vcc. Also, even when the power supply voltage V cc is decreased from 4.0V to 2.5V, the direct-current voltage Vout is kept at the predetermined voltage without any changes before as well as after the change of the power supply voltage Vcc. In addition, to keep the direct-current voltage at the predetermined voltage without an extreme change before as well as after the change of the power supply voltage Vcc, a voltage regulator has been proposed as described in Document 1 (Japanese Patent Publication Laid-open No. 2002-189522).
On the other hand, the above-mentioned voltage regulator operates as described below when the power supply voltage Vcc is changed, for example, in a greater range of 1.3V and 4.0V. When the power supply voltage Vcc is 1.3V, the reference voltage Vref is 1.0V, but the predetermined direct-current voltage Vout is 1.3V at a maximum because the predetermined direct-current voltage Vout can not exceed the power supply voltage Vcc. Accordingly, the comparison voltage Vcom does not exceed 0.8V because the threshold voltage of the NMOS transistor 42 is 0.5V. As a result, the control voltage Vcon is decreased to be an extremely low voltage (for example, 0.3V) which substantially shorts the PMOS transistor 41.
Then, after the power supply voltage Vcc is changed from 1.3V to 4.0V, the electrical potential on the node N2, that is, the control voltage Vcon is increased by the capacitance between the gate electrode and the source electrode of the PMOS transistor 41 responsive to the change of the power supply voltage Vcc. Since the PMOS transistor 41 is substantially shorted as stated above, the increase of the control voltage Vcon can not increase an ON-state resistance of the PMOS transistor 41. Therefore, the direct-current voltage Vout is increased by exceeding the predetermined voltage of 1.5V responsive to the great increase of the power supply voltage Vcc. After that, the direct-current voltage Vout is steadied down to the predetermined voltage of 1.5V.
In order to adjust to the above-mentioned change of the power supply voltage Vcc, it is necessary to allow a large current to pass through the differential amplifier 30. However, in the voltage regulator which realizes low power consumption, the great change of the power supply voltage Vcc generates an extreme variation of the direct-current voltage Vout by which the direct-current voltage Vout largely exceeds the predetermined voltage.